Diff for /wikisrc/users/macallan/crime.mdwn between versions 1.1 and 1.2

version 1.1, 2009/10/21 23:20:05 version 1.2, 2009/10/21 23:21:19
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 This is the rendering engine, memory controller etc. found in [SGI](http://www.sgi.com/)'s [[O2]] workstations. NetBSD has hardware accelerated drivers for both the kernel ( [[crmfb]] ) and [[Xorg]] ( [[xf86-video-crime]] ).<br>  This is the rendering engine, memory controller etc. found in [SGI](http://www.sgi.com/)'s [[O2]] workstations. NetBSD has hardware accelerated drivers for both the kernel ( [[crmfb]] ) and [[Xorg]] ( [[xf86-video-crime]] ).<br>
 Video memory is allocated from main memory in chunks of 64KB which, depending on pixel size, result in 128x128, 256x128 or 512x128 tiles. Output is handled by either [[GBE]] for the VGA port or [[mace]] and the AV module for composite video or s-video ( we don't support TV output yet ).<br>  Video memory is allocated from main memory in chunks of 64KB which, depending on pixel size, result in 128x128, 256x128 or 512x128 tiles. Output is handled by either [[GBE]] for the VGA port or [[mace]] and the AV module for composite video or s-video ( we don't support TV output yet ).<br>
 The drawing engine has two parts - the main Rendering Engine which supports all kinds of fancy operations including alpha blending, z-buffering and whatnot, and the Memory Transfer Engine which only supports simple fills and copies but is rally, really fast.<br>  The drawing engine has two parts - the main Rendering Engine which supports all kinds of fancy operations including alpha blending, z-buffering and whatnot, and the Memory Transfer Engine which only supports simple fills and copies but does them really, really fast ( at memory bandwidth speed according to the docs we have ).<br>
 Both engines share a set of TLBs:  Both engines share a set of TLBs:
   
 * Three TLBs map tiled buffers with up to 16x16 tiles. Entries are the upper 16 bit of each tile's physical address so tiles have to be 64KB-aligned.  * Three TLBs map tiled buffers with up to 16x16 tiles. Entries are the upper 16 bit of each tile's physical address so tiles have to be 64KB-aligned.

Removed from v.1.1  
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  Added in v.1.2


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