Diff for /wikisrc/ports/evbarm/tegra.mdwn between versions 1.30 and 1.40

version 1.30, 2015/11/12 13:26:20 version 1.40, 2017/04/13 20:32:07
Line 34  The NetBSD tegra port currently supports Line 34  The NetBSD tegra port currently supports
    - RF kill switch     - RF kill switch
    - Power button     - Power button
  - AS3722 power management unit   - AS3722 power management unit
    - eFUSE
    - SoC thermal sensors
   
   
 # TODO  # TODO
  - Analog audio output (I2S, Audio codec, APB DMA)   - Memory controller SMMU support
    - APB DMA
    - Audio Hub (AHUB)
  - GPU (nouveau)   - GPU (nouveau)
  - USB 3.0 [[!template id=man name="xhci" section="4"]] controller   - USB 3.0 [[!template id=man name="xhci" section="4"]] controller
  - SPI controller   - SPI controller
  - PWM controller   - PWM controller
  - PCIe MSI support   - PCIe MSI support
    - CL-DVFS
    - LVDS/eDP display output
   
 # Generating a boot script  # Generating a boot script
   
   The Tegra kernels need a .dtb for your board to boot. The dtb here was updated on 2017-04-13 and is generated from a Linux 4.10.10 source tree. [NVIDIA Jetson TK1 .dtb](http://ftp.netbsd.org/pub/NetBSD/misc/jmcneill/tegra/tegra124-jetson-tk1.dtb)
   
 [[!template  id=programlisting text="""  [[!template  id=programlisting text="""
 $ cat boot.txt  $ cat boot.txt
 setenv bootargs root=ld1a  setenv bootargs root=ld1a
 fatload mmc 1:1 0x90000000 netbsd.ub  fatload mmc 1:1 0x90000000 netbsd.ub
 bootm 0x90000000  fatload mmc 1:1 ${fdt_addr_r} tegra124-jetson-tk1.dtb
   fdt addr ${fdt_addr_r}
   bootm 0x90000000 - ${fdt_addr_r}
 $ mkubootimage -A arm -C none -O netbsd -T script -a 0 -n "NetBSD/tegra boot" boot.txt boot.scr  $ mkubootimage -A arm -C none -O netbsd -T script -a 0 -n "NetBSD/tegra boot" boot.txt boot.scr
 """]]  """]]
   
Line 60  Jetson TK1 boards come with Linux4Tegra  Line 70  Jetson TK1 boards come with Linux4Tegra 
   
 # Modesetting  # Modesetting
   
   ## Console
   
   To override the default video mode (auto-detected from display EDID), use the *video* kernel command-line parameter:
   
   [[!template  id=programlisting text="""
   video=<xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
   """]]
   
   ## Xorg
   
 To be able to use the mode setting features of the Tegra DRM driver, you must use the xf86-video-modesetting driver. Put this in xorg.conf:  To be able to use the mode setting features of the Tegra DRM driver, you must use the xf86-video-modesetting driver. Put this in xorg.conf:
   
 [[!template  id=programlisting text="""  [[!template  id=programlisting text="""
Line 78  Copyright (c) 1996, 1997, 1998, 1999, 20 Line 98  Copyright (c) 1996, 1997, 1998, 1999, 20
 Copyright (c) 1982, 1986, 1989, 1991, 1993  Copyright (c) 1982, 1986, 1989, 1991, 1993
     The Regents of the University of California.  All rights reserved.      The Regents of the University of California.  All rights reserved.
   
 NetBSD 7.99.21 (JETSONTK1) #258: Thu Nov 12 06:45:09 AST 2015  NetBSD 7.99.23 (JETSONTK1) #657: Sun Dec 13 12:33:17 AST 2015
         jmcneill@megatron.local:/Users/jmcneill/netbsd/src/sys/arch/evbarm/compile/obj/JETSONTK1          jmcneill@megatron.local:/Users/jmcneill/netbsd/src/sys/arch/evbarm/compile/obj/JETSONTK1
 total memory = 2047 MB  total memory = 2047 MB
 avail memory = 2021 MB  avail memory = 2020 MB
 sysctl_createv: sysctl_create(machine_arch) returned 17  sysctl_createv: sysctl_create(machine_arch) returned 17
 timecounter: Timecounters tick every 10.000 msec  timecounter: Timecounters tick every 10.000 msec
 mainbus0 (root)  mainbus0 (root)
 cpu0 at mainbus0 core 0: 2292 MHz Cortex-A15 r3p3 (Cortex V7A core)  cpu0 at mainbus0 core 0: 2316 MHz Cortex-A15 r3p3 (Cortex V7A core)
 cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled  cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
 cpu0: 32KB/64B 2-way L1 PIPT Instruction cache  cpu0: 32KB/64B 2-way L1 PIPT Instruction cache
 cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache  cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache
Line 100  armgic0: 32 Priorities, 160 SPIs, 7 PPIs Line 120  armgic0: 32 Priorities, 160 SPIs, 7 PPIs
 armgtmr0 at armperiph0: ARMv7 Generic 64-bit Timer (12000 kHz)  armgtmr0 at armperiph0: ARMv7 Generic 64-bit Timer (12000 kHz)
 armgtmr0: interrupting on irq 27  armgtmr0: interrupting on irq 27
 timecounter: Timecounter "armgtmr0" frequency 12000000 Hz quality 500  timecounter: Timecounter "armgtmr0" frequency 12000000 Hz quality 500
 tegraio0 at mainbus0: Tegra K1 (T124)  tegrafdt0 at mainbus0
 tegracar0 at tegraio0: CAR  fdt0 at tegrafdt0: NVIDIA Tegra124 Jetson TK1
 tegracar0: PLLX = 2292000000 Hz  gic0 at fdt0: GIC
 tegracar0: PLLC = 88000000 Hz  tegralic0 at fdt0: LIC
 tegracar0: PLLE = 292968 Hz  tegracar0 at fdt0: CAR
 tegracar0: PLLU = 480000000 Hz  clock at fdt0 not configured
 tegracar0: PLLP0 = 408000000 Hz  tegrampio0 at fdt0: MPIO
 tegracar0: PLLD2 = 594000000 Hz  tegragpio0 at fdt0: GPIO
 tegragpio0 at tegraio0: GPIO  
 gpio0 at tegragpio0 (A): 8 pins  gpio0 at tegragpio0 (A): 8 pins
 gpio1 at tegragpio0 (B): 8 pins  gpio1 at tegragpio0 (B): 8 pins
 gpio2 at tegragpio0 (C): 8 pins  gpio2 at tegragpio0 (C): 8 pins
Line 126  gpio13 at tegragpio0 (N): 8 pins Line 145  gpio13 at tegragpio0 (N): 8 pins
 gpio14 at tegragpio0 (O): 8 pins  gpio14 at tegragpio0 (O): 8 pins
 gpio15 at tegragpio0 (P): 8 pins  gpio15 at tegragpio0 (P): 8 pins
 gpio16 at tegragpio0 (Q): 8 pins  gpio16 at tegragpio0 (Q): 8 pins
 gpiobutton0 at gpio16 pins 0: Power button  
 gpio17 at tegragpio0 (R): 8 pins  gpio17 at tegragpio0 (R): 8 pins
 gpio18 at tegragpio0 (S): 8 pins  gpio18 at tegragpio0 (S): 8 pins
 gpio19 at tegragpio0 (T): 8 pins  gpio19 at tegragpio0 (T): 8 pins
Line 134  gpio20 at tegragpio0 (U): 8 pins Line 152  gpio20 at tegragpio0 (U): 8 pins
 gpio21 at tegragpio0 (V): 8 pins  gpio21 at tegragpio0 (V): 8 pins
 gpio22 at tegragpio0 (W): 8 pins  gpio22 at tegragpio0 (W): 8 pins
 gpio23 at tegragpio0 (X): 8 pins  gpio23 at tegragpio0 (X): 8 pins
 gpiorfkill0 at gpio23 pins 7  
 gpio24 at tegragpio0 (Y): 8 pins  gpio24 at tegragpio0 (Y): 8 pins
 gpio25 at tegragpio0 (Z): 8 pins  gpio25 at tegragpio0 (Z): 8 pins
 gpio26 at tegragpio0 (AA): 8 pins  gpio26 at tegragpio0 (AA): 8 pins
Line 142  gpio27 at tegragpio0 (BB): 8 pins Line 159  gpio27 at tegragpio0 (BB): 8 pins
 gpio28 at tegragpio0 (CC): 8 pins  gpio28 at tegragpio0 (CC): 8 pins
 gpio29 at tegragpio0 (DD): 8 pins  gpio29 at tegragpio0 (DD): 8 pins
 gpio30 at tegragpio0 (EE): 8 pins  gpio30 at tegragpio0 (EE): 8 pins
 tegratimer0 at tegraio0: Timers  simplebus0 at fdt0: regulators
 tegratimer0: default watchdog period is 10 seconds  fdt1 at simplebus0
 tegramc0 at tegraio0: MC  fregulator0 at fdt1: +VDD_MUX
 tegrapmc0 at tegraio0: PMC  fregulator1 at fdt1: +5V_SYS
 tegraxusbpad0 at tegraio0: XUSB PADCTL  fregulator2 at fdt1: +3.3V_SYS
 tegrampio0 at tegraio0: MPIO  fregulator3 at fdt1: +3.3V_RUN
 tegrai2c0 at tegraio0 port 0: I2C1  fregulator4 at fdt1: +3.3V_AVDD_HDMI_AP_GATED
 tegrai2c0: interrupting on irq 70  fregulator5 at fdt1: +USB0_VBUS_SW
   fregulator6 at fdt1: +5V_USB_HS
   fregulator7 at fdt1: +3.3V_LP0
   fregulator8 at fdt1: +1.05V_RUN_AVDD_HDMI_PLL
   fregulator9 at fdt1: +5V_HDMI_CON
   fregulator10 at fdt1: +5V_SATA
   fregulator11 at fdt1: +12V_SATA
   dma at fdt0 not configured
   tegrapmc0 at fdt0: PMC
   tegramc0 at fdt0: MC
   tegramc0: interrupting on LIC irq 109
   tegrai2c0 at fdt0: I2C1
   tegrai2c0: interrupting on LIC irq 70
 iic0 at tegrai2c0: I2C bus  iic0 at tegrai2c0: I2C bus
 seeprom0 at iic0 addr 0x56: AT24Cxx or compatible EEPROM: size 256  audio-codec at iic0 addr 0x1c not configured
 titemp0 at iic0 addr 0x4c: TMP451  titemp0 at iic0 addr 0x4c: TMP451
 tegrai2c1 at tegraio0 port 1: I2C2  seeprom0 at iic0 addr 0x56: eeprom: size 256
 tegrai2c1: interrupting on irq 116  tegrai2c1 at fdt0: I2C2
   tegrai2c1: interrupting on LIC irq 116
 iic1 at tegrai2c1: I2C bus  iic1 at tegrai2c1: I2C bus
 tegrai2c2 at tegraio0 port 2: I2C3  tegrai2c2 at fdt0: I2C3
 tegrai2c2: interrupting on irq 124  tegrai2c2: interrupting on LIC irq 124
 iic2 at tegrai2c2: I2C bus  iic2 at tegrai2c2: I2C bus
 tegrai2c3 at tegraio0 port 3: I2C4  tegrai2c3 at fdt0: I2C4
 tegrai2c3: interrupting on irq 152  tegrai2c3: interrupting on LIC irq 152
 iic3 at tegrai2c3: I2C bus  iic3 at tegrai2c3: I2C bus
 ddc0 at iic3 addr 0x50: DDC  tegrai2c4 at fdt0: I2C5
 tegrai2c4 at tegraio0 port 4: I2C5  tegrai2c4: interrupting on LIC irq 85
 tegrai2c4: interrupting on irq 85  
 iic4 at tegrai2c4: I2C bus  iic4 at tegrai2c4: I2C bus
 as3722pmic0 at iic4 addr 0x40: AMS AS3822  as3722pmic0 at iic4 addr 0x40: AMS AS3822
 com3 at tegraio0 port 3: ns16550a, working fifo  as3722pmic0: default watchdog period is 10 seconds
 com3: console  tegrausbphy0 at fdt0: USB PHY2
 tegrartc0 at tegraio0: RTC  tegrausbphy1 at fdt0: USB PHY3
 sdhc2 at tegraio0 port 2: SDMMC3  tegrapcie0 at fdt0: PCIE
 sdhc2: interrupting on irq 51  tegrapcie0: interrupting on LIC irq 130
 sdhc2: SDHC 4.0, rev 3, 32-bit ADMA2, 204000 kHz, HS SDR50 SDR104 HS200 1.8V 3.0V 3.3V, re-tuning mode 1, 4096 byte blocks  
 sdmmc2 at sdhc2 slot 0  
 sdhc3 at tegraio0 port 3: SDMMC4  
 sdhc3: interrupting on irq 63  
 sdhc3: SDHC 4.0, rev 3, 32-bit ADMA2, 204000 kHz, HS SDR50 SDR104 HS200 1.8V 3.0V 3.3V, re-tuning mode 1, 4096 byte blocks  
 sdmmc3 at sdhc3 slot 0  
 ahcisata0 at tegraio0: SATA  
 ahcisata0: interrupting on irq 55  
 ahcisata0: AHCI revision 1.31, 2 ports, 32 slots, CAP 0xe620ff01<PSC,SSC,PMD,ISS=0x2=Gen2,SAL,SALP,SSNTF,SNCQ,S64A>  
 atabus0 at ahcisata0 channel 0  
 hdaudio0 at tegraio0: HDA  
 hdaudio0: interrupting on irq 113  
 hdafg0 at hdaudio0: NVIDIA Tegra124 HDMI  
 hdafg0: HDMI00 8ch: Digital Out [Jack]  
 hdafg0: 8ch/0ch 44100Hz PCM16*  
 audio0 at hdafg0: full duplex, playback, capture, mmap, independent  
 tegracec0 at tegraio0: HDMI CEC  
 tegracec0: interrupting on irq 35  
 hdmicec0 at tegracec0  
 tegrausbphy0 at tegraio0 port 0: USB PHY1  
 ehci0 at tegraio0 port 0: USB1  
 ehci0: interrupting on irq 52  
 ehci0: EHCI version 1.10  
 ehci0: switching to host mode  
 usb0 at ehci0: USB revision 2.0  
 tegrausbphy1 at tegraio0 port 1: USB PHY2  
 ehci1 at tegraio0 port 1: USB2  
 ehci1: interrupting on irq 53  
 ehci1: EHCI version 1.10  
 ehci1: switching to host mode  
 usb1 at ehci1: USB revision 2.0  
 tegrausbphy2 at tegraio0 port 2: USB PHY3  
 ehci2 at tegraio0 port 2: USB3  
 ehci2: interrupting on irq 129  
 ehci2: EHCI version 1.10  
 ehci2: switching to host mode  
 usb2 at ehci2: USB revision 2.0  
 tegrahost1x0 at tegraio0: HOST1X  
 tegradrm0 at tegraio0  
 drm: Supports vblank timestamp caching Rev 2 (21.10.2013).  
 drm: No driver support for vblank timestamp query.  
 tegrafb0 at tegradrm0  
 tegrafb0: framebuffer at 0x9ab00000, size 1280x720, depth 32, stride 5120  
 wsdisplay0 at tegrafb0 kbdmux 1  
 wsmux1: connecting to wsdisplay0  
 wsdisplay0: screen 0-3 added (default, vt100 emulation)  
 tegradrm0: info: registered panic notifier  
 tegradrm0: initialized tegra 0.1.0 20151108 on minor 0  
 tegrapcie0 at tegraio0: PCIE  
 tegrapcie0: interrupting on irq 130  
 pci0 at tegrapcie0 bus 0  pci0 at tegrapcie0 bus 0
 pci0: memory space enabled, rd/line, rd/mult, wr/inv ok  pci0: i/o space, memory space enabled, rd/line, rd/mult, wr/inv ok
 ppb0 at pci0 dev 0 function 0: vendor 10de product 0e12 (rev. 0xa1)  ppb0 at pci0 dev 0 function 0: vendor 10de product 0e12 (rev. 0xa1)
 ppb0: PCI Express capability version 2 <Root Port of PCI-E Root Complex> x2 @ 5.0GT/s  ppb0: PCI Express capability version 2 <Root Port of PCI-E Root Complex> x2 @ 5.0GT/s
 ppb0: link is x1 @ 2.5GT/s  ppb0: link is x1 @ 2.5GT/s
 pci1 at ppb0 bus 1  pci1 at ppb0 bus 1
 pci1: memory space enabled, rd/line, wr/inv ok  pci1: i/o space, memory space enabled, rd/line, wr/inv ok
 athn0 at pci1 dev 0 function 0athn0: Atheros AR9285  athn0 at pci1 dev 0 function 0: Atheros AR9285
 athn0: rev 2 (1T1R), ROM rev 13, address 00:17:c4:d7:d0:58  athn0: rev 2 (1T1R), ROM rev 13, address 00:17:c4:d7:d0:58
 athn0: interrupting at irq 130  athn0: interrupting at LIC irq 130
 athn0: 11b rates: 1Mbps 2Mbps 5.5Mbps 11Mbps  athn0: 11b rates: 1Mbps 2Mbps 5.5Mbps 11Mbps
 athn0: 11g rates: 1Mbps 2Mbps 5.5Mbps 11Mbps 6Mbps 9Mbps 12Mbps 18Mbps 24Mbps 36Mbps 48Mbps 54Mbps  athn0: 11g rates: 1Mbps 2Mbps 5.5Mbps 11Mbps 6Mbps 9Mbps 12Mbps 18Mbps 24Mbps 36Mbps 48Mbps 54Mbps
 ppb1 at pci0 dev 1 function 0: vendor 10de product 0e13 (rev. 0xa1)  ppb1 at pci0 dev 1 function 0: vendor 10de product 0e13 (rev. 0xa1)
 ppb1: PCI Express capability version 2 <Root Port of PCI-E Root Complex> x1 @ 5.0GT/s  ppb1: PCI Express capability version 2 <Root Port of PCI-E Root Complex> x1 @ 5.0GT/s
 ppb1: link is x1 @ 2.5GT/s  ppb1: link is x1 @ 2.5GT/s
 pci2 at ppb1 bus 2  pci2 at ppb1 bus 2
 pci2: memory space enabled, rd/line, wr/inv ok  pci2: i/o space, memory space enabled, rd/line, wr/inv ok
 re0 at pci2 dev 0 function 0: RealTek 8168/8111 PCIe Gigabit Ethernet (rev. 0x0c)  re0 at pci2 dev 0 function 0: RealTek 8168/8111 PCIe Gigabit Ethernet (rev. 0x0c)
 re0: interrupting at irq 130  re0: interrupting at LIC irq 130
 re0: Ethernet address 00:04:4b:2f:51:a2  re0: Ethernet address 00:04:4b:2f:51:a2
 re0: using 512 tx descriptors  re0: using 512 tx descriptors
 rgephy0 at re0 phy 7: RTL8251 1000BASE-T media interface, rev. 0  rgephy0 at re0 phy 7: RTL8251 1000BASE-T media interface, rev. 0
 rgephy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT-FDX, auto  rgephy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT-FDX, auto
   tegradrm0 at fdt0
   drm: Supports vblank timestamp caching Rev 2 (21.10.2013).
   drm: No driver support for vblank timestamp query.
   tegrafb0 at tegradrm0
   tegrafb0: framebuffer at 0x9bc00000, size 1920x1080, depth 32, stride 7680
   wsdisplay0 at tegrafb0 kbdmux 1
   wsmux1: connecting to wsdisplay0
   wsdisplay0: screen 0-3 added (default, vt100 emulation)
   tegradrm0: info: registered panic notifier
   tegradrm0: initialized tegra 0.1.0 20151108 on minor 0
   tegratimer0 at fdt0: Timers
   tegratimer0: default watchdog period is 10 seconds
   flow-controller at fdt0 not configured
   actmon at fdt0 not configured
   apbmisc at fdt0 not configured
   com0 at fdt0: ns16550a, working fifo
   com0: console
   com0: interrupting on LIC irq 122
   spi at fdt0 not configured
   spi at fdt0 not configured
   tegrartc0 at fdt0: RTC
   tegrafuse0 at fdt0: FUSE
   emc at fdt0 not configured
   ahcisata0 at fdt0: SATA
   ahcisata0: couldn't acquire vddio-supply
   ahcisata0: couldn't acquire avdd-supply
   ahcisata0: interrupting on LIC irq 55
   ahcisata0: AHCI revision 1.31, 2 ports, 32 slots, CAP 0xe620ff01<PSC,SSC,PMD,ISS=0x2=Gen2,SAL,SALP,SSNTF,SNCQ,S64A>
   atabus0 at ahcisata0 channel 0
   hdaudio0 at fdt0: HDA
   hdaudio0: interrupting on LIC irq 113
   hdafg0 at hdaudio0: NVIDIA Tegra124 HDMI
   hdafg0: HDMI00 8ch: Digital Out [Jack]
   hdafg0: 8ch/0ch 44100Hz PCM16*
   audio0 at hdafg0: full duplex, playback, capture, mmap, independent
   tegraxusbpad0 at fdt0: XUSB PADCTL
   sdhc0 at fdt0: SDMMC3
   sdhc0: interrupting on LIC irq 51
   sdhc0: SDHC 4.0, rev 3, 32-bit ADMA2, 204000 kHz, HS SDR50 SDR104 HS200 1.8V 3.0V 3.3V, re-tuning mode 1, 4096 byte blocks
   sdmmc0 at sdhc0 slot 0
   sdhc1 at fdt0: SDMMC4
   sdhc1: interrupting on LIC irq 63
   sdhc1: SDHC 4.0, rev 3, 32-bit ADMA2, 204000 kHz, HS SDR50 SDR104 HS200 1.8V 3.0V 3.3V, re-tuning mode 1, 4096 byte blocks
   sdmmc1 at sdhc1 slot 0
   tegrasoctherm0 at fdt0: SOC_THERM
   ahub at fdt0 not configured
   ehci0 at fdt0: USB2
   ehci0: interrupting on LIC irq 53
   ehci0: EHCI version 1.10
   ehci0: switching to host mode
   usb0 at ehci0: USB revision 2.0
   ehci1 at fdt0: USB3
   ehci1: interrupting on LIC irq 129
   ehci1: EHCI version 1.10
   ehci1: switching to host mode
   usb1 at ehci1: USB revision 2.0
   pmu at fdt0 not configured
   timer at fdt0 not configured
   simplebus1 at fdt0: clocks
   fdt2 at simplebus1
   clock at fdt2 not configured
   gpio-keys at fdt0 not configured
   sound at fdt0 not configured
 timecounter: Timecounter "clockinterrupt" frequency 100 Hz quality 0  timecounter: Timecounter "clockinterrupt" frequency 100 Hz quality 0
 cpu2: 2292 MHz Cortex-A15 r3p3 (Cortex V7A core)  cpu3: 2316 MHz Cortex-A15 r3p3 (Cortex V7A core)
 cpu2: DC enabled IC enabled WB disabled EABT branch prediction enabled  
 cpu2: 32KB/64B 2-way L1 PIPT Instruction cache  
 cpu2: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache  
 cpu2: 2048KB/64B 16-way write-through L2 PIPT Unified cache  
 vfp2 at cpu2: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals  
 cpu1: 2292 MHz Cortex-A15 r3p3 (Cortex V7A core)  
 cpu1: DC enabled IC enabled WB disabled EABT branch prediction enabled  
 cpu1: 32KB/64B 2-way L1 PIPT Instruction cache  
 cpu1: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache  
 cpu1: 2048KB/64B 16-way write-through L2 PIPT Unified cache  
 vfp1 at cpu1: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals  
 cpu3: 2292 MHz Cortex-A15 r3p3 (Cortex V7A core)  
 cpu3: DC enabled IC enabled WB disabled EABT branch prediction enabled  cpu3: DC enabled IC enabled WB disabled EABT branch prediction enabled
 cpu3: 32KB/64B 2-way L1 PIPT Instruction cache  cpu3: 32KB/64B 2-way L1 PIPT Instruction cache
 cpu3: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache  cpu3: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache
 cpu3: 2048KB/64B 16-way write-through L2 PIPT Unified cache  cpu3: 2048KB/64B 16-way write-through L2 PIPT Unified cache
 vfp3 at cpu3: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals  vfp3 at cpu3: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
   cpu1: 2316 MHz Cortex-A15 r3p3 (Cortex V7A core)
   cpu1: DC enabled IC enabled WB disabled EABT branch prediction enabled
   cpu1: 32KB/64B 2-way L1 PIPT Instruction cache
   cpu1: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache
   cpu1: 2048KB/64B 16-way write-through L2 PIPT Unified cache
   vfp1 at cpu1: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
   cpu2: 2316 MHz Cortex-A15 r3p3 (Cortex V7A core)
   cpu2: DC enabled IC enabled WB disabled EABT branch prediction enabled
   cpu2: 32KB/64B 2-way L1 PIPT Instruction cache
   cpu2: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache
   cpu2: 2048KB/64B 16-way write-through L2 PIPT Unified cache
   vfp2 at cpu2: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
 uhub0 at usb0: Tegra EHCI root hub, class 9/0, rev 2.00/1.00, addr 1  uhub0 at usb0: Tegra EHCI root hub, class 9/0, rev 2.00/1.00, addr 1
 uhub0: 1 port with 1 removable, self powered  uhub0: 1 port with 1 removable, self powered
   ahcisata0 port 0: device present, speed: 3.0Gb/s
 uhub1 at usb1: Tegra EHCI root hub, class 9/0, rev 2.00/1.00, addr 1  uhub1 at usb1: Tegra EHCI root hub, class 9/0, rev 2.00/1.00, addr 1
 uhub1: 1 port with 1 removable, self powered  uhub1: 1 port with 1 removable, self powered
 uhub2 at usb2: Tegra EHCI root hub, class 9/0, rev 2.00/1.00, addr 1  sdhc1: cmd timeout error
 uhub2: 1 port with 1 removable, self powered  
 sdhc3: cmd timeout error  
 IPsec: Initialized Security Association Processing.  IPsec: Initialized Security Association Processing.
 ahcisata0 port 0: device present, speed: 3.0Gb/s  ld0 at sdmmc1: <0x45:0x0100:SEM16G:0x00:0x0301ff34:0x000>
 ld0 at sdmmc3: <0x45:0x0100:SEM16G:0x00:0x0301ff34:0x000>  
 ld0: 15028 MB, 7633 cyl, 64 head, 63 sec, 512 bytes/sect x 30777344 sectors  ld0: 15028 MB, 7633 cyl, 64 head, 63 sec, 512 bytes/sect x 30777344 sectors
 ld0: GPT GUID: a81e231f-7b1c-c564-1473-5ac55e4b7963  ld0: GPT GUID: a81e231f-7b1c-c564-1473-5ac55e4b7963
 dk0 at ld0: "APP", 29360128 blocks at 94208, type: <unknown>  dk0 at ld0: "APP", 29360128 blocks at 94208, type: <unknown>
 ld1 at sdmmc2: <0x27:0x5048:SD64G:0x30:0x01ce4def:0x0dc>  
 dk1 at ld0: "DTB", 8192 blocks at 29454336, type: <unknown>  dk1 at ld0: "DTB", 8192 blocks at 29454336, type: <unknown>
 dk2 at ld0: "EFI", 131072 blocks at 29462528, type: <unknown>  ld1 at sdmmc0dk2 at ld0: "EFI", 131072 blocks at 29462528, type: <unknown>
   : <0x27:0x5048:SD64G:0x30:0x01ce4def:0x0dc>
 dk3 at ld0: "USP", 8192 blocks at 29593600, type: <unknown>  dk3 at ld0: "USP", 8192 blocks at 29593600, type: <unknown>
 dk4 at ld0: "TP1", 8192 blocks at 29601792, type: <unknown>  dk4 at ld0: "TP1", 8192 blocks at 29601792, type: <unknown>
 dk5 at ld0: "TP2", 8192 blocks at 29609984, type: <unknown>  dk5 at ld0: "TP2", 8192 blocks at 29609984, type: <unknown>
Line 295  wd0: drive supports 16-sector PIO transf Line 335  wd0: drive supports 16-sector PIO transf
 wd0: 111 GB, 232581 cyl, 16 head, 63 sec, 512 bytes/sect x 234441648 sectors  wd0: 111 GB, 232581 cyl, 16 head, 63 sec, 512 bytes/sect x 234441648 sectors
 wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133)  wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133)
 wd0(ahcisata0:0:0): using PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133) (using DMA)  wd0(ahcisata0:0:0): using PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133) (using DMA)
 uhidev0 at uhub2 port 1 configuration 1 interface 0  uhidev0 at uhub1 port 1 configuration 1 interface 0
 uhidev0: Logitech USB Receiver, rev 2.00/29.00, addr 2, iclass 3/1  uhidev0: Logitech USB Receiver, rev 2.00/29.00, addr 2, iclass 3/1
 ukbd0 at uhidev0: 8 modifier keys, 6 key codes  ukbd0 at uhidev0: 8 modifier keys, 6 key codes
 wskbd0 at ukbd0 mux 1  wskbd0 at ukbd0 mux 1
 wskbd0: connecting to wsdisplay0  wskbd0: connecting to wsdisplay0
 uhidev1 at uhub2 port 1 configuration 1 interface 1  uhidev1 at uhub1 port 1 configuration 1 interface 1
 uhidev1: Logitech USB Receiver, rev 2.00/29.00, addr 2, iclass 3/1  uhidev1: Logitech USB Receiver, rev 2.00/29.00, addr 2, iclass 3/1
 uhidev1: 17 report ids  uhidev1: 17 report ids
 ums0 at uhidev1 reportid 2: 16 buttons, W and Z dirs  ums0 at uhidev1 reportid 2: 16 buttons, W and Z dirs
Line 312  uhid3 at uhidev1 reportid 17: input=19,  Line 352  uhid3 at uhidev1 reportid 17: input=19, 
 boot device: wd0  boot device: wd0
 root on wd0a dumps on wd0b  root on wd0a dumps on wd0b
 root file system type: ffs  root file system type: ffs
 kern.module.path=/stand/evbarm/7.99.21/modules  kern.module.path=/stand/evbarm/7.99.23/modules
 WARNING: preposterous TOD clock time  WARNING: preposterous TOD clock time
 WARNING: using filesystem time  WARNING: using filesystem time
 WARNING: CHECK AND RESET THE DATE!  WARNING: CHECK AND RESET THE DATE!
Line 323  WARNING: CHECK AND RESET THE DATE! Line 363  WARNING: CHECK AND RESET THE DATE!
 - [NVIDIA Jetson TK1 development kit](https://developer.nvidia.com/jetson-tk1)  - [NVIDIA Jetson TK1 development kit](https://developer.nvidia.com/jetson-tk1)
 - [Hardware documentation](https://developer.nvidia.com/hardware-design-and-development)  - [Hardware documentation](https://developer.nvidia.com/hardware-design-and-development)
 - [Linux For Tegra](https://developer.nvidia.com/linux-tegra)  - [Linux For Tegra](https://developer.nvidia.com/linux-tegra)
   - [Device Tree](http://www.devicetree.org)
   
   .

Removed from v.1.30  
changed lines
  Added in v.1.40


CVSweb for NetBSD wikisrc <wikimaster@NetBSD.org> software: FreeBSD-CVSweb