[[!meta title="NetBSD/evbarm on BeagleBone"]]

[[images/beaglebone.jpg]]

This page attempts to document and coordinate efforts towards NetBSD on [BeagleBone](http://beagleboard.org/bone).

(BeagleBone [image](http://www.flickr.com/photos/sparkfun/8267577194/) by SparkFun Electronics used under CC-By-2.0 license)

# What works
 - Boots multi-user on [[!template id=man name="ld" section="4"]] @ [[!template id=man name="sdmmc" section="4"]] root and [[!template id=man name="com" section="4"]] console.
 - Ethernet ([[!template id=man name="cpsw" section="4" arch="evbarm"]])

# What needs work
 - EDMA3 (perhaps at first for [[!template id=man name="sdhc" section="4"]])
 - USB (host)
 - SPI
 - I²C
 - GPIO
 - Framebuffer/graphics with LCD or DVI/HDMI capes
 - Touchscreens on LCD capes
 - USB (device)

# Sample dmesg
[[!template id=filecontent name="dmesg" text="""
NetBSD 6.99.16 (BEAGLEBONE)
total memory = 256 MB
avail memory = 247 MB
timecounter: Timecounters tick every 10.000 msec
cprng kernel: WARNING insufficient entropy at creation.
mainbus0 (root)
cpu0 at mainbus0 core 0: 720 MHz Cortex-A8 r3p2 (Cortex core)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: isar: [0]=0x101111 [1]=0x13112111 [2]=0x21232031 [3]=0x11112131, [4]=0x11142, [5]=0
cpu0: mmfr: [0]=0x1100003 [1]=0x20000000 [2]=0x1202000 [3]=0x211
cpu0: pfr: [0]=0x1131 [1]=0x11
cpu0: 32KB/64B 4-way L1 Instruction cache
cpu0: 32KB/64B 4-way write-back-locking-C L1 Data cache
cpu0: 256KB/64B 8-way write-through L2 Unified cache
vfp0 at cpu0: NEON MPE (VFP 3.0+)
obio0 at mainbus0 base 0x44000000-0x4fffffff: On-Board IO
omapicu0 at obio0 addr 0x48200000-0x48200fff intrbase 0
prcm0 at obio0 addr 0x44e00000-0x44e01fff: Power, Reset and Clock Management
gpmc0 at mainbus0 base 0x50000000-0x50ffffff: General Purpose Memory Controller, rev 6.0
gpmc0: CS#0 valid, addr 0x08000000, size 256MB
com0 at obio0 addr 0x44e09000-0x44e09fff intr 72: ns16550a, working fifo
com0: console
sdhc0 at obio0 addr 0x48060100-0x48060fff intr 64: SDHC controller
sdhc0: SD Host Specification 2.0, rev.49
sdmmc0 at sdhc0 slot 0
omapdmtimer0 at obio0 addr 0x48040000-0x48040fff intr 68: DMTIMER2
omapdmtimer1 at obio0 addr 0x44e31000-0x44e31fff intr 67: DMTIMER1ms
omapdmtimer2 at obio0 addr 0x48044000-0x48044fff intr 92: DMTIMER4
omapwdt32k0 at obio0 addr 0x44e35000-0x44e35fff: rev 0.1
timecounter: Timecounter "clockinterrupt" frequency 100 Hz quality 0
timecounter: Timecounter "dmtimer" frequency 24000000 Hz quality 100
ld0 at sdmmc0: <0x28:0x4245:31676:0x10::0x0a7>
ld0: 490 MB, 995 cyl, 16 head, 63 sec, 512 bytes/sect x 1003520 sectors
ld0: 4-bit width, bus clock 50.000 MHz
cprng sysctl: WARNING insufficient entropy at creation.
boot device: <unknown>
root on ld0f dumps on ld0b
WARNING: no TOD clock present
WARNING: using filesystem time
WARNING: CHECK AND RESET THE DATE!
init: copying out path `/sbin/init' 11
"""]]